In many digital applications, CMOS (Complementary MOS) static logic circuits have been used which have inherently lower power with higher performance than other NMOS (N-channel Metal Oxide Semiconductor) or PMOS (P-channel Metal Oxide Semiconductor) circuits. However, in case of each CMOS static logic circuit constituted with p-type FET (PFET) and n-type FET (NFET), when the FETs are simultaneously turned on by an input signal, a leakage current flows in the CMOS static logic circuit. For this reason, the CMOS static logic circuit is not suitable for a digital circuit with lower power and high speed operation. In high-speed and low-power application, the conventional CMOS design techniques often impose severe speed and power trade-offs, thereby limiting their design flexibility. This is because the system designers have no choice but to design CMOS circuits having one of the two characteristics, or having balanced characteristics.
Pass-transistor logic (hereinafter, referred to as "PL") circuit comprised of a plurality of n type FETs (NFETs) only, has been proposed as a logic circuit suitable for lower power and high speed operation. This PL circuit carries out the same logic function as a conventional CMOS logic circuit, but the number of its transistors is reduced by half, as compared with the conventional CMOS logic circuit. Therefore, in some instances pass-transistor logics are employed, sparingly, to reduce circuit size without increasing power or losing speed. Introduction of PL circuits to many digital applications can minimize the trade-offs as described above.
As shown in FIG. 1, typical AND/NAND pass-transistor logic circuit 10 is constituted with four NFETs M1 to M4, and has four inputs 12, 14, 16 and 18 and two outputs 20 and 22. Input signal "A" and "/A" of the circuit 10 are applied to the inputs 12 and 14, and another input signal "B" and "/B" thereof to the inputs 16 and 18. Drain of the NFET M1 is connected to the input 12 and gate thereof to the input 16. Source of the NFET M2 is grounded and gate thereof is connected to the input 18. Source of the NFET M1 and drain of the FET M2 are commonly connected to the output 20 of the circuit 10. The NFETs M1 and M2 provide the logical ANDing function of the two inputs "A" and "B", thereby resulting in A.cndot.B through the output 20.
Also, the drain of the NFET M3 is connected to a supply voltage V.sub.DD and the gate thereof to the input 18 of the circuit 10. Drain of the NFET M4 is connected to the input 14 and gate thereof to the input 16. Sources of the NFETs M3 and M4 are commonly connected to the output 22 of the circuit 10. The NFETs M3 and M4 provide the logical NANDing function of the two inputs "A" and "B", thereby resulting in /A.cndot.B through the output 22 of the circuit 10.
In the AND/NAND pass-transistor logic circuit 10 as described above, when both the inputs "A" and "B" are logical "1" or high, the NFETs M1 and M4 are turned on. Thus, A.cndot.B=1 and /A.cndot.B="0". If both the inputs are logical "0" or low, or when the input "A" is high and the input "B" is low, the NFETs M2 and M3 are turned on. Thus, A.cndot.B=0 and /A.cndot.B=1. When the input "A" goes low and the input "B" goes high, the NFETs M1 and M4 are turned on, resulting in A.cndot.B=0 and /A.cndot.B=1.
As stated immediately above, the PL circuit 10 has lower power with higher performance than the CMOS logic circuit. This is because the input signals thereof are simultaneously applied to gates and drains of the NFETs constituting the PL circuit. In the conventional PL circuit 10, however, when the output is "1" or high, voltage level of the output is not increased up to a strong or full high level, e.g., V.sub.DD, but it is insufficiently increased up to V.sub.DD -Vt (where Vt is threshold voltage of an NFET). The reduction of the output voltage causes a circuit noise margin to be seriously lowered, resulting in decrease in circuit performance. Accordingly, the conventional PL logic requires a level restoration circuit for restoring the output from an insufficient high level to a V.sub.DD. This PL logic having a level restoration circuit is disclosed by K. Yano, et al., in Proc. IEEE 1994 CICC, May 1994, pp. 603-606, entitled "Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs". As reported in the art, the complementary pass-transistor logic (CPL) circuit is shown in FIG. 2.
As shown in FIG. 2, besides the PL circuit 10 of FIG. 1, the complementary PL (hereinafter, referred to as "CPL") further comprises a level restoration circuit 24. The level restoration circuit 24 consists of two CMOS inverters 26 and 28, and has two outputs 30 and 32. Input of the CMOS inverter 26 is connected to one 20 of the outputs of the PL circuit 10 and input of the CMOS inverter 28 is connected to the other output 32.
Operation of the CPL having the above described configuration will be described hereinafter. For brief description, the outputs A.cndot.B and /A.cndot.B of the PL circuit 10 are hereinafter called "AND output" and "NAND output", respectively. When the AND output of the PL circuit 10 is low, PFET Qp1 of the CMOS inverter 26 is turned on. Thus, the output 30 has a strong or full high level. Therefore, a system using the CPL circuit has an improved function, as compared with another system without the CPL circuit.
In the CPL circuit of FIG. 2, however, the NAND output of the PL circuit 10 becomes a weak high level, V.sub.DD -Vt. NFET Qn2 of the inverter 28 is incompletely turned on so that a signal of weak low level is generated from the output 32. Also, since the PFET Qp2 is not completely turned off, a small leakage current flows therethrough. The power consumption of the CPL circuit is large while the operation speed thereof is kept high. A good description on the subject is found in an article entitled "A High Speed, Low Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Application" by A. Parameswar, et al., in Proc. IEEE 1994 CICC, May 1994, pp. 278-281.
FIG. 3 shows a Swing Restored Pass-Transistor Logic (SRPL) circuit disclosed in the above mentioned article. The SRPL circuit of FIG. 3, like the CPL circuit of FIG. 2, has a level restoration circuit 34 which consist of two CMOS inverters 36 and 38. In the SRPL circuit, the outputs 20 and 22 of the PL circuit 10 are connected to outputs 40 and 42 of the level restoration circuit 34, respectively. Input of one of the two CMOS inverters is connected to output of the other. In detail, the output 40 of the inverter 36 is connected to the input of the inverter 38 and the output 42 of the inverter 38 to the input of the inverter 36. When in the SRPL circuit the AND output of the PL circuit 10 is weak high level (V.sub.DD -Vt), NAND output signal of strong or full low level is provided from the PL circuit 10 to the level restoration circuit 34. Then, PFET Qp3 of the inverter 36 is completely turned on so that AND output of strong or full high level V.sub.DD is generated from the output 40 of the level restoration circuit 34. As a result, PFET Qp4 of the inverter 38 is completely turned off and thereby a leakage current does not flow through the PFET Qp4.
As described immediately above, the SRPL circuit has an excellent level restoration function, but a voltage of high level on the output 40 or 42 is discharged through the PL circuit 10. Since the logic circuit has the above described PL function block in which a plurality of NFETs of multi-stage are serially connected, as in a full adder, it has a longer discharge time. As a result, a delay time is increased.
Additionally, as shown in FIG. 6, the SRPL circuit hardly operates in case that each NFET constituting it is small in size. In FIG. 6, X-axis indicates a size of each NFET constituting the PL circuit 10, i.e., a Width/Length (W/L) ratio, and Y-axis indicates a delay time. "1" on the X-axis depicts an NFET size, W/L=1.7/0.65, and "3" thereon depicts W/L=5.1/0.65. It can be understood from FIG. 6 that each NFET of the SRPL circuit must have three or four times in size than the standard NFET in order to normally operate.
As described above, the SRPL circuit has an excellent level restoration function, but can not be formed with high density logic.